Designing Correct Circuits 2010
20-21 March 2010, Paphos, Cyprus
A satellite event of the ETAPS 2010 group of conferences

Abstracts due: Monday 23 November 2009
Notification of acceptance: Monday 21 December 2009
Final version: Wednesday 20 January 2010

The Workshop:
About DCC'10
(Programme, including presented slides)
(Pre-Proceedings)

Call for papers:
PDF version
Text version

Programme Committee:
Arvind, MIT
Per Bjesse, Synopsys
Wolfgang Kunz, University of Kaiserslautern
Bob Kurshan, Cadence Design Systems
Pete Manolios, Northeastern University
Andy Martin, IBM
Tom Melham, University of Oxford
Gordon Pace, University of Malta
Marc Pouzet, University of Paris-Sud
Carl Seger, Intel
Satnam Singh, Microsoft Research
Joe Stoy, Bluespec

Contact:
Joe Stoy

Programme

(Click on a title to see the slides used in the presentation. Note that the titles are those used for the presentations, and are sometimes different from those appearing in the pre-proceedings.) Saturday 20th March 2010
	*Formal Approaches*
09:00-09:45	Formal Validation and Verification of Networks-on-Chips: Status and Perspective Julien Schmaltz, Freek Verbeek, Tom van den Broek (Open University of The Netherlands)
09:45-10:30	A Formalised Framework for Incremental Modelling of On-Chip Communication Peter Boehm (University of Oxford)
10:30-11:00	Coffee Break
11:00-11:45	Gap-Free verification of weakly programmable IPs against their operational ISA model Markus Wedler, Sacha Loitz, Wolfgang Kunz (University of Kaiserslautern)
11:45-12:30	A Prototype Embedding of Bluespec SystemVerilog in the SAL Model Checker Dominic Richards, David Lester (University of Manchester)
12:30-14:00	Lunch
	*Bluespec SystemVerilog*
14:00-14:45	Living With Kind #: Improving the Usability of Numeric Types in Bluespec SystemVerilog Joe Stoy (for Ravi Nanavati)
14:45-15:30	Checking Modular Refinements of Bluespec Nirav Dave (Massachusetts Institute of Technology), Michael Katelman (University of Illinois at Urbana-Champaign)

Sunday 21st March 2010
	*Languages*
09:00-09:45	A Proposal for a More Generic, More Accountable, Verilog Cherif Salama, Walid Taha (Rice University)
09:45-10:30	A Meta-Language for Hardware Testbench Michael Katelman and Jose Meseguer (University of Illinois at Urbana-Champaign)
10:30-11:00	Coffee Break
11:00-11:45	Clock typing of n-Synchronous Programs Louis Mandel, Florence Plateau, Marc Pouzet (Universite Paris-Sud and INRIA)
11:45-12:30	DISCUSSION
12:30-14:00	Lunch
	*Design and Synthesis*
14:00-14:45	Synthesis of Data-Parallel GPU Software into FPGA Hardware Satnam Singh (Microsoft Coroporation)
14:45-15:30	Functional programming and hardware design: where to now?? Wouter Swierstra, Koen Claessen, Carl Seger, Mary Sheeran, Emily Shriver (Chalmers UniversitY of Technology and Intel Coroporation)