Computer Architecture: 2010-2011
Lecturer | |
Degrees | Schedule S1(3rd years) — Computer Science |
Term | Trinity Term 2011 (16 lectures) |
Overview
This course aims to give an understanding of the mechanisms for implementing the programmer's idealised computer. It builds on the introduction to hardware and to simple processors in the Digital Systems course. The Computer Architecture course aims to describe a broad range of architectural designs and to contrast them, highlighting the design decisions they incorporate. The designs are described and analysed at the register-transfer level of abstraction.
Practicals
Processor simulation exercises.
Learning outcomes
By the end of the course, the student should understand the major architectural styles and appreciate the compromises that they encapsulate. They should be able to read outline descriptions of real processors and understand in which way their designs fit into the frameworks described in the course. They should also be able to understand the impact of design choices in programming in the context of a specific architecture.Synopsis
- Datapaths and control structures for processors, register transfer level description of hardware
- Design and Simulation in Verilog and C++/SystemC
- Instruction set design, instruction formats, addressing modes, ISAs
- A simple RISC design
- A simple x86 (CISC) design, microcode
- Processor pipelining, pipeline hazards
- Hazard detection, forwarding
- Branch prediction and other kinds of speculation
- Out-of-order execution and register renaming
- Reorder buffers
- Virtual Memory, virtualization
- Main and cache memories
- Multi-cores and cache coherency
- Direct memory access and peripherals, systems on chip (SoC)
- Architectures without shared memory
- Revision
Syllabus
Register Transfer model of processors. Datapaths and control structures. Comparison of architectural styles for general purpose computers, including RISC/CISC. Pipelining; pipeline hazards and their resolution by stalling and forwarding. Techniques for executing more than one instruction in each clock cycle. The hierarchy of storage in a computer; caches and virtual memory. Styles of parallel computers, and their implementation in contemporary designs.Reading list
Principal texts; either one of:
- D A Patterson & J L Hennessy, Computer Organization and Design: the hardware/software interface, Morgan-Kaufmann (Fourth edition) 2009.
- D A Patterson & J L Hennessy, Computer Organization and Design: the hardware/software interface, Morgan-Kaufmann (Third edition, revised printing) 2007.
The fourth edition covers more recent designs and is preferred; only the third edition covers multi-cycle designs. Either one should be adequate, if available. Similarly, the second edition is relevant if available, but may be confusing.
Background reading:
- Some articles (to be identified near the time of the course) about contemporary designs.
- K. Stevens et al., An Asynchronous Instruction Length Decoder
- R.M. Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units
Feedback
Students are formally asked for feedback at the end of the course. Students can also submit feedback at any point here. Feedback received here will go to the Head of Academic Administration, and will be dealt with confidentially when being passed on further. All feedback is welcome.
Taking our courses
This form is not to be used by students studying for a degree in the Department of Computer Science, or for Visiting Students who are registered for Computer Science courses
Other matriculated University of Oxford students who are interested in taking this, or other, courses in the Department of Computer Science, must complete this online form by 17.00 on Friday of 0th week of term in which the course is taught. Late requests, and requests sent by email, will not be considered. All requests must be approved by the relevant Computer Science departmental committee and can only be submitted using this form.