ETAPS 2010 Designing Correct Circuits 2010
20-21 March 2010, Paphos, Cyprus
A satellite event of the ETAPS 2010 group of conferences


Abstracts due: Monday 23 November 2009
Notification of acceptance: Monday 21 December 2009
Final version: Wednesday 20 January 2010
The Workshop:
About DCC'10
(Programme, including presented slides)
(Pre-Proceedings)


Call for papers:
PDF version
Text version


Programme Committee:
Arvind, MIT
Per Bjesse, Synopsys
Wolfgang Kunz, University of Kaiserslautern
Bob Kurshan, Cadence Design Systems
Pete Manolios, Northeastern University
Andy Martin, IBM
Tom Melham, University of Oxford
Gordon Pace, University of Malta
Marc Pouzet, University of Paris-Sud
Carl Seger, Intel
Satnam Singh, Microsoft Research
Joe Stoy, Bluespec


Contact:
Joe Stoy

The Eighth International Workshop on Designing Correct Circuits will be held in March 2010 in Paphos, Cypus, as a satellite event of ETAPS 2010. Previous workshops in the informal DCC series were held in Oxford (1990), Lyngby (1992), Båstad (1996), Grenoble (2002), Barcelona (2004), Vienna (2006) and Budapest (2008). These meetings were all very stimulating events, and each made a contribution to building our research community.

In recent years formal methods have been increasingly used in the verification of large-scale circuit designs, particularly in the microprocessor industry. Great progress has been made in adapting and scaling up methods developed in academia, and in developing new methods to solve real verification problems. Various themes emerged in the field ranging from ways to compose design and verification to system level modelling. A variety of useful tools have been developed, theorem provers, model checkers and combinations of the two. Similarly, the use of higher-level hardware design languages, including functional ones, has been explored, and various approaches and solutions have appeared.

But more needs to be done. There are indications that we need to incorporate formal verification earlier in the design process, and this means thinking hard about our design and specification notations, and about how best to guide the verification process. We should probably exploit modern programming language technology, and we need to think about how to raise the level of abstraction at which we do verification. The aim of the workshop is to present the state of the art in hardware design and verification methods (from both an academic and an industrial viewpoint). Then, we hope to start a discussion on the question of what needs to be done next in research if we are to solve the huge problems facing both microprocessor manufacturers and the System-on-a-Chip development, and in the automotive and aerospace industries. We particularly hope that many doctoral students will attend the workshop and be enthused by this fascinating research area that lies on the border between academia and industry.

The 2010 DCC workshop aims at bringing together a stimulating mix of academic and industrial researchers in formal methods for hardware design and verification, stimulating discussion about the current state of the art in formally-based hardware verification and how more effective design and verification methods can be developed.